Generally, a QFN (quad flat non-leaded) semiconductor package is basically configured by mounting at least a chip on a die pad of a lead frame, and forming a plurality of conductive elements such as bonding wires for electrically connecting the chip to leads of the lead frame, wherein the chip, bonding wires and lead frame are encapsulated by an encapsulating resin to form an encapsulant. As compared with a QFP (quad flat package) having outer leads that are exposed to outside of the package and used to establish external electrical connection, this QFN semiconductor package, as named, is characterized to be free of exposed outer leads, and thus relatively lower in overall package profile. Moreover, the QFN semiconductor package is adapted to expose bottom surfaces of the die pad and leads to outside of the encapsulant. These exposed surfaces directly urge the semiconductor package to be electrically coupled to an external device such as a printed circuit board (PCB), by which no other conductive elements e.g. solder balls or bumps are necessarily provided for the semiconductor package to serve as I/O (input/output) connections for communicating with the external device, making process complexity and costs of fabrication both considerably reduced.
However, the above conventional QFN semiconductor package is still inherent with significant drawbacks, for example, relatively weak bonding between the encapsulant and lead frame, bridging of adjacent leads during singulation, and so on. This is because that, as described above, the die pad and leads of the QFN semiconductor package are partly exposed and not entirely enclosed by the encapsulant, which thereby weakens bonding strength between the encapsulant and lead frame, and tends to cause delamination between the encapsulant and the die pad or leads, making quality and reliability of the semiconductor package adversely affected.
In accordance with the delamination problem, U.S. Pat. No. 6,081,029 teaches a semiconductor package 1 shown in FIG. 6A. Similar to a conventional QFN semiconductor package, this semiconductor package 1 adopts a lead frame 10 with at least a chip 12 being mounted on a die pad 11 thereof. A plurality of bonding wires 13 are formed to electrically connect the chip 12 to leads 14 of the lead frame 10. All these components of the semiconductor package 1 are encapsulated by an encapsulant 15, wherein bottom surfaces of the die pad 11 and leads 14 are exposed to outside of the encapsulant 15. In particular, the semiconductor package 1 is characterized in forming of a recessed step-like portion 110, which dents upwardly from bottom peripheral edge of the die pad 11, and allows part of the encapsulant 15 to fill into the step-like portion 110, This helps enhancing contact area and bonding strength between the die pad 11 and the encapsulant 15, and thereby reduce the occurrence of delamination.
As shown in FIG. 7A, U.S. Pat. No. 6,229,200 discloses a semiconductor package 2, in which at least a chip 22 is deposited on a die pad 21 of a lead frame 20, and electrically connected to leads 24 of the lead frame 20 by a plurality of bonding wires 23; an encapsulant 25 is formed to encapsulate all the foregoing components of the semiconductor package 2, with bottom surfaces of the die pad 21 and leads 24 being exposed to outside of the encapsulant 25. Similar to the above-described semiconductor package 1, a step-like portion 210 is formed at bottom peripheral edge of the die pad 21 in the semiconductor package 2, so as to reinforce bonding strength between the die pad 21 and the encapsulant 25. Moreover, ends of the leads 24 around the die pad 21 are also formed with step-like portions 240 at bottom edges thereof, by which contact area and bonding strength between the leads 24 and the encapsulant 25 are effectively enhanced. In provision of the step-like portions 210, 240, the lead frame 20 is firmly bonded with the encapsulant 25, and much less likely to delaminate from the encapsulant 25; thereby, reliability of the semiconductor package 2 can be well assured.
However, those above disclosed semiconductor packages are still in concern of the lead bridging problem. During a singulation process, by virtue of metal affinity to a cutting tool, cut-side burrs of the metal-made leads are usually generated when the cutting tool cuts through the leads. As shown in FIGS. 6B and 7B, since the leads 14, 24 of the semiconductor package 1, 2 are densely arranged or low in pitch, cut-side burrs may diffuse along a cutting direction (as indicated by an arrow in the respective drawings) to cause bridging and short-circuiting of adjacent leads, which severely damages quality and yield of singulated products.
Therefore, how to effectively eliminate the drawback of lead bridging caused by diffusion of lead burrs during singulation, and to assure quality and reliability of fabricated products, are significant problems to solve.